libpruio
0.2
Input/Output driver for digital/analog lines on Beagleboard hardware
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P9.bi
Go to the documentation of this file.
1
/'* \file P9.bi
2
\brief Pin settings for P9 header pins.
3
4
This files gets included by pruio_config.bas. It declares the pin
5
settings for all CPU balls connected to the header P9 connectors on
6
Beaglebone hardware.
7
8
'/
9
10
' Load convenience macros.
11
#INCLUDE ONCE
"../pruio/pruio_pins.bi"
12
13
' pin 1, GND
14
' pin 2, GND
15
' pin 3, 3V3
16
' pin 4, 3V3
17
' pin 5, VDD 5V
18
' pin 6, VDD 5V
19
' pin 7, SYS 5V
20
' pin 8, SYS 5V
21
' pin 9, PWR BUT
22
' pin 10, ZCZ ball A10 RESETn
23
24
' ZCZ ball T17
25
M(P9_11) =
CHR
( _
26
0 + _I_ _
' gpmc_wait0
27
, 1 + _I_ _
' gmii2_crs
28
, 2 + _O_ _
' gpmc_csn4
29
, 3 + _I_ _
' rmii2_crs_dv
30
, 4 + _I_ _
' mmc1_sdcd
31
, 5 + _I_ _
' pr1_mii_col
32
, 6 + _I_ _
' uart4_rxd
33
) & GPIO_DEF
34
35
' ZCZ ball U18
36
M(P9_12) =
CHR
( _
37
0 + _O_ _
' gpmc_be1n
38
, 1 + _I_ _
' gmii2_col
39
, 2 + _O_ _
' gpmc_csn6
40
, 3 + I_O _
' mmc2_dat3
41
, 4 + _O_ _
' gpmc_dir
42
, 5 + _I_ _
' pr1_mii_rxlink
43
, 6 + I_O _
' mcasp0_aclkr
44
) & GPIO_DEF
45
46
' ZCZ ball U17
47
M(P9_13) =
CHR
( _
48
0 + _O_ _
' gpmc_wpn
49
, 1 + _I_ _
' gmii2_rxerr
50
, 2 + _O_ _
' gpmc_csn5
51
, 3 + _I_ _
' rmii2_rxerr
52
, 4 + _I_ _
' mmc2_sdcd
53
, 5 + _O_ _
' pr1_mii1_txen
54
, 6 + _O_ _
' uart4_txd
55
) & GPIO_DEF
56
57
' ZCZ ball U14
58
M(P9_14) =
CHR
( _
59
0 + _O_ _
' gpmc_a2
60
, 1 + _O_ _
' gmii2_txd3
61
, 2 + _O_ _
' rgmii2_td3
62
, 3 + I_O _
' mmc2_dat1
63
, 4 + _O_ _
' gpmc_a18
64
, 5 + _O_ _
' pr1_mii1_txd2
65
, 6 + _O_ _
' ehrpwm1A
66
) & GPIO_DEF
67
68
' ZCZ ball R13
69
M(P9_15) =
CHR
( _
70
0 + _O_ _
' gpmc_a0
71
, 1 + _O_ _
' gmii2_txen
72
, 2 + _O_ _
' rgmii2_tctl
73
, 3 + _O_ _
' rmii2_txen
74
, 4 + _O_ _
' gpmc_a16
75
, 5 + _I_ _
' pr1_mii_mt1_clk
76
, 6 + _I_ _
' ehrpwm1_tripzone_input
77
) & GPIO_DEF
78
79
' ZCZ ball T14
80
M(P9_16) =
CHR
( _
81
0 + _O_ _
' gpmc_a3
82
, 1 + _O_ _
' gmii2_txd2
83
, 2 + _O_ _
' rgmii2_td2
84
, 3 + I_O _
' mmc2_dat2
85
, 4 + _O_ _
' gpmc_a19
86
, 5 + _O_ _
' pr1_mii1_txd1
87
, 6 + _O_ _
' ehrpwm1B
88
) & GPIO_DEF
89
90
' ZCZ ball A16
91
M(P9_17) =
CHR
( _
92
0 + I_O _
' spi0_cs0
93
, 1 + _I_ _
' mmc2_sdwp
94
, 2 + IOD _
' I2C1_SCL
95
, 3 + _I_ _
' ehrpwm0_synci
96
, 4 + _O_ _
' pr1_uart0_txd
97
, 5 + _I_ _
' pr1_edio_data_in1
98
, 6 + _O_ _
' pr1_edio_data_out1
99
) & GPIO_DEF
100
101
' ZCZ ball B16
102
M(P9_18) =
CHR
( _
103
0 + I_O _
' spi0_d1
104
, 1 + _I_ _
' mmc1_sdwp
105
, 2 + IOD _
' I2C1_SDA
106
, 3 + _I_ _
' ehrpwm0_tripzone_input
107
, 4 + _I_ _
' pr1_uart0_rxd
108
, 5 + _I_ _
' pr1_edio_data_in0
109
, 6 + _O_ _
' pr1_edio_data_out0
110
) & GPIO_DEF
111
112
' ZCZ ball D17 (i2c)
113
M(P9_19) =
CHR
( _
114
0 + _O_ _
' uart1_rtsn
115
, 1 + TMRi _
' timer5_in
116
, 1 + TMRo _
' timer5_pwm_out
117
, 2 + _I_ _
' dcan0_rx
118
, 3 + IOD _
' I2C2_SCL
119
, 4 + I_O _
' spi1_cs1
120
, 5 + _O_ _
' pr1_uart0_rts_n
121
, 6 + _I_ _
' pr1_edc_latch_in
122
) & GPIO_DEF
123
124
' ZCZ ball D18 (i2c)
125
M(P9_20) =
CHR
( _
126
0 + _I_ _
' uart1_ctsn
127
, 1 + TMRi _
' timer6_in
128
, 1 + TMRo _
' timer6pwm_out
129
, 2 + _O_ _
' dcan0_tx
130
, 3 + IOD _
' I2C2_SDA
131
, 4 + I_O _
' spi1_cs0
132
, 5 + _I_ _
' pr1_uart0_cts_n
133
, 6 + _I_ _
' pr1_edc_latch0_in
134
) & GPIO_DEF
135
136
' ZCZ ball B17
137
M(P9_21) =
CHR
( _
138
0 + I_O _
' spi0_d0
139
, 1 + _O_ _
' uart2_txd
140
, 2 + IOD _
' I2C2_SCL
141
, 3 + _O_ _
' ehrpwm0B
142
, 4 + _O_ _
' pr1_uart0_rts_n
143
, 5 + _I_ _
' pr1_edio_latch_in
144
, 6 + I_O _
' EMU3
145
) & GPIO_DEF
146
147
' ZCZ ball A17
148
M(P9_22) =
CHR
( _
149
0 + I_O _
' spi0_sclk
150
, 1 + _I_ _
' uart2_rxd
151
, 2 + IOD _
' I2C2_SDA
152
, 3 + _O_ _
' ehrpwm0A
153
, 4 + _I_ _
' pr1_uart0_cts_n
154
, 5 + _O_ _
' pr1_edio_sof
155
, 6 + I_O _
' EMU2
156
) & GPIO_DEF
157
158
' ZCZ ball V14
159
M(P9_23) =
CHR
( _
160
0 + _O_ _
' gpmc_a1
161
, 1 + _I_ _
' gmii2_rxdv
162
, 2 + _I_ _
' rgmii2_rctl
163
, 3 + I_O _
' mmc2_dat0
164
, 4 + _O_ _
' gpmc_a17
165
, 5 + _O_ _
' pr1_mii1_txd3
166
, 6 + _O_ _
' ehrpwm0_synco
167
) & GPIO_DEF
168
169
' ZCZ ball d15
170
M(P9_24) =
CHR
( _
171
0 + _O_ _
' uart1_txd
172
, 1 + _I_ _
' mmc2_sdwp
173
, 2 + _I_ _
' dcan1_rx
174
, 3 + IOD _
' I2C1_SCL
175
, 5 + _O_ _
' pr1_uart0_txd
176
, 6 + _I_ _
' pr1_pru0_pru_r31_16
177
) & GPIO_DEF
178
179
' ZCZ ball a14 (AUDIO)
180
M(P9_25) =
CHR
( _
181
0 + I_O _
' mcasp0_ahclkx
182
, 1 + QEPi _
' eQEP0_strobe_in
183
, 1 + QEPo _
' eQEP0_strobe_out
184
, 2 + I_O _
' mcasp0_axr3
185
, 3 + I_O _
' mcasp1_axr1
186
, 4 + I_O _
' EMU4
187
, 5 + _O_ _
' pr1_pru0_pru_r30_7
188
, 6 + _I_ _
' pr1_pru0_pru_r31_7
189
) & GPIO_DEF
190
191
' ZCZ ball D16
192
M(P9_26) =
CHR
( _
193
0 + _I_ _
' uart1_rxd
194
, 1 + _I_ _
' mmc1_sdwp
195
, 2 + _O_ _
' dcan1_tx
196
, 3 + IOD _
' I2C1_SDA
197
, 5 + _I_ _
' pr1_uart0_rxd
198
, 6 + _I_ _
' pr1_pru1_pru_r31_16
199
) & GPIO_DEF
200
201
' ZCZ ball C13
202
M(P9_27) =
CHR
( _
203
0 + I_O _
' mcasp0_fsr
204
, 1 + _I_ _
' eQEP0B_in
205
, 2 + I_O _
' mcasp0_axr3
206
, 3 + I_O _
' mcasp1_fsx
207
, 4 + I_O _
' EMU2
208
, 5 + _O_ _
' pr1_pru0_pru_r30_5
209
, 6 + _I_ _
' pr1_pru0_pru_r31_5
210
) & GPIO_DEF
211
212
' ZCZ ball C12
213
M(P9_28) =
CHR
( _
214
0 + I_O _
' mcasp0_ahclkr
215
, 1 + _I_ _
' ehrpwm0_synci
216
, 2 + I_O _
' mcasp0_axr2
217
, 3 + I_O _
' spi1_cs0
218
, 4 + CAPo _
' eCAP2_PWM2_out
219
, 4 + CAPi _
' eCAP2_in
220
, 5 + _O_ _
' pr1_pru0_pru_r30_3
221
, 6 + _I_ _
' pr1_pru0_pru_r31_3
222
) & GPIO_DEF
223
224
' ZCZ ball B13 (audio)
225
M(P9_29) =
CHR
( _
226
0 + I_O _
' mcasp0_fsx
227
, 1 + _O_ _
' ehrpwm0B
228
, 3 + I_O _
' spi1_d0
229
, 4 + _I_ _
' mmc1_sdcd
230
, 5 + _O_ _
' pr1_pru0_pru_r30_1
231
, 6 + _I_ _
' pr1_pru0_pru_r31_1
232
) & GPIO_DEF
233
234
' ZCZ ball D12
235
M(P9_30) =
CHR
( _
236
0 + I_O _
' mcasp0_axr0
237
, 1 + _I_ _
' ehrpwm0_tripzone_input
238
, 3 + I_O _
' spi1_d1
239
, 4 + _I_ _
' mmc2_sdcd
240
, 5 + _O_ _
' pr1_pru0_pru_r30_2
241
, 6 + _I_ _
' pr1_pru0_pru_r31_2
242
) & GPIO_DEF
243
244
' ZCZ ball A13 (audio)
245
M(P9_31) =
CHR
( _
246
0 + I_O _
' mcasp0_aclkx
247
, 1 + _O_ _
' ehrpwm0A
248
, 3 + I_O _
' spi1_sclk
249
, 4 + _I_ _
' mmc0_sdcd
250
, 5 + _O_ _
' pr1_pru0_pru_r30_0
251
, 6 + _I_ _
' pr1_pru0_pru_r31_0
252
) & GPIO_DEF
253
254
'pin 32, (ADC VAC)
255
'pin 33, ZCZ ball C8 (ADC AIN-4)
256
'pin 34, (ADC AGND)
257
'pin 35, ZCZ ball A8 (ADC AIN-6)
258
'pin 36, ZCZ ball B8 (ADC AIN-5)
259
'pin 37, ZCZ ball B7 (ADC AIN-2)
260
'pin 38, ZCZ ball A7 (ADC AIN-3)
261
'pin 39, ZCZ ball B6 (ADC AIN-0)
262
'pin 40, ZCZ ball C7 (ADC AIN-1)
263
264
' ZCZ ball D14 (mcasp)
265
M(P9_41) =
CHR
( _
266
0 + _I_ _
' xdma_event_intr1
267
, 2 + _I_ _
' tclkin
268
, 3 + _O_ _
' clkout2
269
, 4 + TMRi _
' timer7_in
270
, 4 + TMRo _
' timer7_pwm_out
271
, 5 + _I_ _
' pr1_pru0_pru_r31_16
272
, 6 + I_O _
' EMU3
273
) & GPIO_DEF
274
275
' ZCZ ball C18
276
M(P9_42) =
CHR
( _
277
0 + CAPo _
' eCAP0_PWM0_out
278
, 0 + CAPi _
' eCAP0_in
279
, 1 + _O_ _
' uart3_txd
280
, 2 + I_O _
' spi1_cs1
281
, 3 + CAPi _
' pr1_ecap0_ecap_capin
282
, 3 + CAPo _
' pr1_ecap0_ecap_apwm_o
283
, 4 + I_O _
' spi1_sclk
284
, 5 + _I_ _
' mmc0_sdwp
285
, 6 + _I_ _
' xdma_event_intr2
286
) & GPIO_DEF
287
288
' pin 41, ZCZ ball D13 (mcasp)
289
M(106) =
CHR
( _
290
0 + I_O _
' mcasp0_axr1
291
, 1 + QEPi _
' eQEP0_index_in
292
, 1 + QEPo _
' eQEP0_index_out
293
, 3 + I_O _
' mcasp1_axr0
294
, 4 + I_O _
' EMU3
295
, 5 + _O_ _
' pr1_pru0_pru_r30_6
296
, 6 + _I_ _
' pr1_pru0_pru_r31_6
297
) & GPIO_DEF
298
299
' pin 42, ZCZ ball B12
300
M(104) =
CHR
( _
301
0 + I_O _
' mcasp0_aclkr
302
, 1 + _I_ _
' eQEP0A_in
303
, 2 + I_O _
' mcasp0_axr2
304
, 3 + I_O _
' mcasp1_aclkx
305
, 4 + _I_ _
' mmc0_sdwp
306
, 5 + _O_ _
' pr1_pru0_pru_r30_4
307
, 6 + _I_ _
' pr1_pru0_pru_r31_4
308
) & GPIO_DEF
309
310
'pin 43, GND
311
'pin 44, GND
312
'pin 45, GND
313
'pin 46, GND
314
src
config
P9.bi
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