libpruio
0.2
Input/Output driver for digital/analog lines on Beagleboard hardware
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P8.bi
Go to the documentation of this file.
1
/'* \file P8.bi
2
\brief Pin settings for P8 header pins.
3
4
This files gets included by pruio_config.bas. It declares the pin
5
settings for all CPU balls connected to the header P8 connectors on
6
Beaglebone hardware.
7
8
'/
9
10
' Load convenience macros.
11
#INCLUDE ONCE
"../pruio/pruio_pins.bi"
12
13
' pin 01, GND
14
' pin 02, GND
15
16
' ZCZ ball R9 (emmc)
17
M(P8_03) =
CHR
( _
18
0 + I_O _
' gpmc_ad6
19
, 1 + I_O _
' mmc1_dat6
20
) & GPIO_DEF
21
22
' ZCZ ball T9 (emmc)
23
M(P8_04) =
CHR
( _
24
0 + I_O _
' gpmc_ad7
25
, 1 + I_O _
' mmc1_dat7
26
) & GPIO_DEF
27
28
' ZCZ ball R8 (emmc)
29
M(P8_05) =
CHR
( _
30
0 + I_O _
' gpmc_ad2
31
, 1 + I_O _
' mmc1_dat2
32
) & GPIO_DEF
33
34
' ZCZ ball T8 (emmc)
35
M(P8_06) =
CHR
( _
36
0 + I_O _
' gpmc_ad3
37
, 1 + I_O _
' mmc1_dat3
38
) & GPIO_DEF
39
40
' ZCZ ball R7
41
M(P8_07) =
CHR
( _
42
0 + _O_ _
' gpmc_advn_ale
43
, 2 + TMRi _
' timer4_in
44
, 2 + TMRo _
' timer4_pwm_out
45
) & GPIO_DEF
46
47
' ZCZ ball T7
48
M(P8_08) =
CHR
( _
49
0 + _O_ _
' gpmc_oen_ren
50
, 2 + TMRi _
' timer7_in
51
, 2 + TMRo _
' timer7_pwm_out
52
) & GPIO_DEF
53
54
' ZCZ ball T6
55
M(P8_09) =
CHR
( _
56
0 + _O_ _
' gpmc_be0n_cle
57
, 2 + TMRi _
' timer5_in
58
, 2 + TMRo _
' timer5_pwm_out
59
) & GPIO_DEF
60
61
' ZCZ ball U6
62
M(P8_10) =
CHR
( _
63
0 + _O_ _
' gpmc_wen
64
, 2 + TMRi _
' timer6_in
65
, 2 + TMRo _
' timer6_pwm_out
66
) & GPIO_DEF
67
68
' ZCZ ball R12
69
M(P8_11) =
CHR
( _
70
0 + I_O _
' gpmc_ad13
71
, 1 + _O_ _
' lcd_data18
72
, 2 + I_O _
' mmc1_dat5
73
, 3 + I_O _
' mmc2_dat1
74
, 4 + _I_ _
' eQEP2B_in
75
, 5 + _O_ _
' pr1_mii0_txd1
76
, 6 + _O_ _
' pr1_pru0_pru_r30_15
77
) & GPIO_DEF
78
79
' ZCZ ball T12
80
M(P8_12) =
CHR
( _
81
0 + I_O _
' gpmc_ad12
82
, 1 + _O_ _
' lcd_data19
83
, 2 + I_O _
' mmc1_dat4
84
, 3 + I_O _
' mmc2_dat0
85
, 4 + _I_ _
' eQEP2A_in
86
, 5 + _O_ _
' pr1_mii0_txd2
87
, 6 + _O_ _
' pr1_pru0_pru_r30_14
88
) & GPIO_DEF
89
90
' ZCZ ball T10
91
M(P8_13) =
CHR
( _
92
0 + I_O _
' gpmc_ad9
93
, 1 + _O_ _
' lcd_data22
94
, 2 + I_O _
' mmc1_dat1
95
, 3 + I_O _
' mmc2_dat5
96
, 4 + _O_ _
' ehrpwm2B
97
, 5 + _I_ _
' pr1_mii0_col
98
) & GPIO_DEF
99
100
' ZCZ ball T11
101
M(P8_14) =
CHR
( _
102
0 + I_O _
' gpmc_ad10
103
, 1 + _O_ _
' lcd_data21
104
, 2 + I_O _
' mmc1_dat2
105
, 3 + I_O _
' mmc2_dat6
106
, 4 + _I_ _
' ehrpwm2_tripzone_input
107
, 5 + _O_ _
' pr1_mii0_txen
108
) & GPIO_DEF
109
110
' ZCZ ball U13
111
M(P8_15) =
CHR
( _
112
0 + I_O _
' gpmc_ad15
113
, 1 + _O_ _
' lcd_data16
114
, 2 + I_O _
' mmc1_dat7
115
, 3 + I_O _
' mmc2_dat3
116
, 4 + QEPi _
' eQEP2_strobe_in
117
, 4 + QEPo _
' eQEP2_strobe_out
118
, 5 + CAPi _
' pr1_ecap0_ecap_capin
119
, 5 + CAPo _
' pr1_ecap0_ecap_apwm_o
120
, 6 + _I_ _
' pr1_pru0_pru_r31_15
121
) & GPIO_DEF
122
123
' ZCZ ball V13
124
M(P8_16) =
CHR
( _
125
0 + I_O _
' gpmc_ad14
126
, 1 + _O_ _
' lcd_data17
127
, 2 + I_O _
' mmc1_dat6
128
, 3 + I_O _
' mmc2_dat2
129
, 4 + QEPi _
' eQEP2_index_in
130
, 4 + QEPo _
' eQEP2_index_out
131
, 5 + _O_ _
' pr1_mii0_txd0
132
, 6 + _I_ _
' pr1_pru0_pru_r31_14
133
) & GPIO_DEF
134
135
' ZCZ ball U12
136
M(P8_17) =
CHR
( _
137
0 + I_O _
' gpmc_ad11
138
, 1 + _O_ _
' lcd_data20
139
, 2 + I_O _
' mmc1_dat3
140
, 3 + I_O _
' mmc2_dat7
141
, 4 + _O_ _
' ehrpwm0_synco
142
, 5 + _O_ _
' pr1_mii0_txd3
143
) & GPIO_DEF
144
145
' ZCZ ball V12
146
M(P8_18) =
CHR
( _
147
0 + I_O _
' gpmc_clk
148
, 1 + _O_ _
' lcd_memory_clk
149
, 2 + _I_ _
' gpmc_wait1
150
, 3 + I_O _
' mmc2_clk
151
, 4 + _I_ _
' pr1_mii1_crs
152
, 5 + _O_ _
' pr1_mdio_mdclk
153
, 6 + I_O _
' mcasp0_fsr
154
) & GPIO_DEF
155
156
' ZCZ ball U10
157
M(P8_19) =
CHR
( _
158
0 + I_O _
' gpmc_ad8
159
, 1 + _O_ _
' lcd_data23
160
, 2 + I_O _
' mmc1_dat0
161
, 3 + I_O _
' mmc2_dat4
162
, 4 + _O_ _
' ehrpwm2A
163
, 5 + _I_ _
' pr1_mii_mt0_clk
164
) & GPIO_DEF
165
166
' ZCZ ball V9 (emmc)
167
M(P8_20) =
CHR
( _
168
0 + _O_ _
' gpmc_csn2
169
, 1 + _O_ _
' gpmc_be1n
170
, 2 + I_O _
' mmc1_cmd
171
, 3 + _I_ _
' pr1_edio_data_in7
172
, 4 + _O_ _
' pr1_edio_data_out7
173
, 5 + _O_ _
' pr1_pru1_pru_r30_13
174
, 6 + _I_ _
' pr1_pru1_pru_r31_13
175
) & GPIO_DEF
176
177
' ZCZ ball U9 (emmc)
178
M(P8_21) =
CHR
( _
179
0 + _O_ _
' gpmc_csn1
180
, 1 + I_O _
' gpmc_clk
181
, 2 + I_O _
' mmc1_clk
182
, 3 + _I_ _
' pr1_edio_data_in6
183
, 4 + _O_ _
' pr1_edio_data_out6
184
, 5 + _O_ _
' pr1_pru1_pru_r30_12
185
, 6 + _I_ _
' pr1_pru1_pru_r31_12
186
) & GPIO_DEF
187
188
' ZCZ ball V8 (emmc)
189
M(P8_22) =
CHR
( _
190
0 + I_O _
' gpmc_ad5
191
, 1 + I_O _
' mmc1_dat5
192
) & GPIO_DEF
193
194
' ZCZ ball U8 (emmc)
195
M(P8_23) =
CHR
( _
196
0 + I_O _
' gpmc_ad4
197
, 1 + I_O _
' mmc1_dat4
198
) & GPIO_DEF
199
200
' ZCZ ball V7 (emmc)
201
M(P8_24) =
CHR
( _
202
0 + I_O _
' gpmc_ad1
203
, 1 + I_O _
' mmc1_dat1
204
) & GPIO_DEF
205
206
' ZCZ ball U7 (emmc)
207
M(P8_25) =
CHR
( _
208
0 + I_O _
' gpmc_ad0
209
, 1 + I_O _
' mmc1_dat0
210
) & GPIO_DEF
211
212
' ZCZ ball V6
213
M(P8_26) =
CHR
( _
214
0 + _O_ _
' gpmc_csn0
215
) & GPIO_DEF
216
217
' ZCZ ball U5 (hdmi)
218
M(P8_27) =
CHR
( _
219
0 + _O_ _
' lcd_vsync
220
, 1 + _O_ _
' gpmc_a8
221
, 2 + _O_ _
' gpmc_a1
222
, 3 + _I_ _
' pr1_edio_data_in2
223
, 4 + _O_ _
' pr1_edio_data_out2
224
, 5 + _O_ _
' pr1_pru1_pru_r30_8
225
, 6 + _I_ _
' pr1_pru1_pru_r31_8
226
) & GPIO_DEF
227
228
' ZCZ ball V5 (hdmi)
229
M(P8_28) =
CHR
( _
230
0 + _O_ _
' lcd_pclk
231
, 1 + _O_ _
' gpmc_a10
232
, 2 + _I_ _
' pr1_mii0_crs
233
, 3 + _I_ _
' pr1_edio_data_in4
234
, 4 + _O_ _
' pr1_edio_data_out4
235
, 5 + _O_ _
' pr1_pru1_pru_r30_10
236
, 6 + _I_ _
' pr1_pru1_pru_r31_10
237
) & GPIO_DEF
238
239
' ZCZ ball R5
240
M(P8_29) =
CHR
( _
241
0 + _O_ _
' lcd_hsync
242
, 1 + _O_ _
' gpmc_a9
243
, 2 + _O_ _
' gpmc_a2
244
, 3 + _I_ _
' pr1_edio_data_in3
245
, 4 + _O_ _
' pr1_edio_data_out3
246
, 5 + _O_ _
' pr1_pru1_pru_r30_9
247
, 6 + _I_ _
' pr1_pru1_pru_r31_9
248
) & GPIO_DEF
249
250
' ZCZ ball R6 (hdmi)
251
M(P8_30) =
CHR
( _
252
0 + _O_ _
' lcd_ac_bias_en
253
, 1 + _O_ _
' gpmc_a11
254
, 2 + _I_ _
' pr1_mii1_crs
255
, 3 + _I_ _
' pr1_edio_data_in5
256
, 4 + _O_ _
' pr1_edio_data_out5
257
, 5 + _O_ _
' pr1_pru1_pru_r30_11
258
, 6 + _I_ _
' pr1_pru1_pru_r30_11
259
) & GPIO_DEF
260
261
' ZCZ ball V4 (hdmi)
262
M(P8_31) =
CHR
( _
263
0 + I_O _
' lcd_data14
264
, 1 + _O_ _
' gpmc_a18
265
, 2 + QEPi _
' eQEP1_index_in
266
, 2 + QEPo _
' eQEP1_index_out
267
, 3 + I_O _
' mcasp0_axr1
268
, 4 + _I_ _
' uart5_rxd
269
, 5 + _I_ _
' pr1_mii_mr0_clk
270
, 6 + _I_ _
' uart5_ctsn
271
) & GPIO_DEF
272
273
' ZCZ ball T5 (hdmi)
274
M(P8_32) =
CHR
( _
275
0 + I_O _
' lcd_data15
276
, 1 + _O_ _
' gpmc_a19
277
, 2 + QEPi _
' eQEP1_strobe_in
278
, 2 + QEPo _
' eQEP1_strobe_out
279
, 3 + I_O _
' mcasp0_ahclkx
280
, 4 + I_O _
' mcasp0_axr3
281
, 5 + _I_ _
' pr1_mii0_rxdv
282
, 6 + _O_ _
' uart5_rtsn
283
) & GPIO_DEF
284
285
' ZCZ ball V3 (hdmi)
286
M(P8_33) =
CHR
( _
287
0 + I_O _
' lcd_data13
288
, 1 + _O_ _
' gpmc_a17
289
, 2 + _I_ _
' eQEP1B_in
290
, 3 + I_O _
' mcasp0_fsr
291
, 4 + I_O _
' mcasp0_axr3
292
, 5 + _I_ _
' pr1_mii0_rxer
293
, 6 + _O_ _
' uart4_rtsn
294
) & GPIO_DEF
295
296
' ZCZ ball U4 (hdmi)
297
M(P8_34) =
CHR
( _
298
0 + I_O _
' lcd_data11
299
, 1 + _O_ _
' gpmc_a15
300
, 2 + _O_ _
' ehrpwm1B
301
, 3 + I_O _
' mcasp0_ahclkr
302
, 4 + I_O _
' mcasp0_axr2
303
, 5 + _I_ _
' pr1_mii0_rxd0
304
, 6 + _O_ _
' uart3_rtsn
305
) & GPIO_DEF
306
307
' ZCZ ball V2 (hdmi)
308
M(P8_35) =
CHR
( _
309
0 + I_O _
' lcd_data12
310
, 1 + _O_ _
' gpmc_a16
311
, 2 + _I_ _
' eQEP1A_in
312
, 3 + I_O _
' mcasp0_aclkr
313
, 4 + I_O _
' mcasp0_axr2
314
, 5 + _I_ _
' pr1_mii0_rxlink
315
, 6 + _I_ _
' uart4_ctsn
316
) & GPIO_DEF
317
318
' ZCZ ball U3 (hdmi)
319
M(P8_36) =
CHR
( _
320
0 + I_O _
' lcd_data10
321
, 1 + _O_ _
' gpmc_a14
322
, 2 + _O_ _
' ehrpwm1A
323
, 3 + I_O _
' mcasp0_axr0
324
, 5 + _I_ _
' pr1_mii0_rxd1
325
, 6 + _I_ _
' uart3_ctsn
326
) & GPIO_DEF
327
328
' ZCZ ball U1 (hdmi)
329
M(P8_37) =
CHR
( _
330
0 + I_O _
' lcd_data8
331
, 1 + _O_ _
' gpmc_a12
332
, 2 + _I_ _
' ehrpwm1_tripzone_input
333
, 3 + I_O _
' mcasp0_aclkx
334
, 4 + _O_ _
' uart5_txd
335
, 5 + _I_ _
' pr1_mii0_rxd3
336
, 6 + _I_ _
' uart2_ctsn
337
) & GPIO_DEF
338
339
' ZCZ ball U2 (hdmi)
340
M(P8_38) =
CHR
( _
341
0 + I_O _
' lcd_data9
342
, 1 + _O_ _
' gpmc_a13
343
, 2 + _O_ _
' ehrpwm0_synco
344
, 3 + I_O _
' mcasp0_fsx
345
, 4 + _I_ _
' uart5_rxd
346
, 5 + _I_ _
' pr1_mii0_rxd2
347
, 6 + _O_ _
' uart2_rtsn
348
) & GPIO_DEF
349
350
' ZCZ ball T3 (hdmi)
351
M(P8_39) =
CHR
( _
352
0 + I_O _
' lcd_data6
353
, 1 + _O_ _
' gpmc_a6
354
, 2 + _I_ _
' pr1_edio_data_in6
355
, 3 + QEPi _
' eQEP2_index_in
356
, 3 + QEPo _
' eQEP2_index_out
357
, 4 + _O_ _
' pr1_edio_data_out6
358
, 5 + _O_ _
' pr1_pru1_pru_r30_6
359
, 6 + _I_ _
' pr1_pru1_pru_r31_6
360
) & GPIO_DEF
361
362
' ZCZ ball T4 (hdmi)
363
M(P8_40) =
CHR
( _
364
0 + I_O _
' lcd_data7
365
, 1 + _O_ _
' gpmc_a7
366
, 2 + _I_ _
' pr1_edio_data_in7
367
, 3 + QEPi _
' eQEP2_strobe_in
368
, 3 + QEPo _
' eQEP2_strobe_out
369
, 4 + _O_ _
' pr1_edio_data_out7
370
, 5 + _O_ _
' pr1_pru1_pru_r30_7
371
, 6 + _I_ _
' pr1_pru1_pru_r31_7
372
) & GPIO_DEF
373
374
' ZCZ ball T1 (hdmi)
375
M(P8_41) =
CHR
( _
376
0 + I_O _
' lcd_data4
377
, 1 + _O_ _
' gpmc_a4
378
, 2 + _O_ _
' pr1_mii0_txd1
379
, 3 + _I_ _
' eQEP2A_in
380
, 5 + _O_ _
' pr1_pru1_pru_r30_4
381
, 6 + _I_ _
' pr1_pru1_pru_r31_4
382
) & GPIO_DEF
383
384
' ZCZ ball T2 (hdmi)
385
M(P8_42) =
CHR
( _
386
0 + I_O _
' lcd_data5
387
, 1 + _O_ _
' gpmc_a5
388
, 2 + _O_ _
' pr1_mii0_txd0
389
, 3 + _I_ _
' eQEP2B_in
390
, 5 + _O_ _
' pr1_pru1_pru_r30_5
391
, 6 + _I_ _
' pr1_pru1_pru_r31_5
392
) & GPIO_DEF
393
394
' ZCZ ball R3 (hdmi)
395
M(P8_43) =
CHR
( _
396
0 + I_O _
' lcd_data2
397
, 1 + _O_ _
' gpmc_a2
398
, 2 + _O_ _
' pr1_mii0_txd3
399
, 3 + _I_ _
' ehrpwm2_tripzone_input
400
, 5 + _O_ _
' pr1_pru1_pru_r30_2
401
, 6 + _I_ _
' pr1_pru1_pru_r31_2
402
) & GPIO_DEF
403
404
' ZCZ ball R4 (hdmi)
405
M(P8_44) =
CHR
( _
406
0 + I_O _
' lcd_data3
407
, 1 + _O_ _
' gpmc_a3
408
, 2 + _O_ _
' pr1_mii0_txd2
409
, 3 + _O_ _
' ehrpwm0_synco
410
, 5 + _O_ _
' pr1_pru1_pru_r30_3
411
, 6 + _I_ _
' pr1_pru1_pru_r31_3
412
) & GPIO_DEF
413
414
' ZCZ ball R1 (hdmi)
415
M(P8_45) =
CHR
( _
416
0 + I_O _
' lcd_data0
417
, 1 + _O_ _
' gpmc_a0
418
, 2 + _I_ _
' pr1_mii_mt0_clk
419
, 3 + _O_ _
' ehrpwm2A
420
, 5 + _O_ _
' pr1_pru1_pru_r30_0
421
, 6 + _I_ _
' pr1_pru1_pru_r31_0
422
) & GPIO_DEF
423
424
' ZCZ ball R2 (hdmi)
425
M(P8_46) =
CHR
( _
426
0 + I_O _
' lcd_data1
427
, 1 + _O_ _
' gpmc_a1
428
, 2 + _O_ _
' pr1_mii0_txen
429
, 3 + _O_ _
' ehrpwm2B
430
, 5 + _O_ _
' pr1_pru1_pru_r30_1
431
, 6 + _I_ _
' pr1_pru1_pru_r31_1
432
) & GPIO_DEF
433
434
src
config
P8.bi
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